;SimSam 1.0
;by Dan Green, 4ms Pedals
;unveiled at Handmade Music Austin #4, Jan 17, 2010

.include "tn85def.inc"

.EQU MYRAMSTART = 0x0070
.EQU MYRAMEND = 0x0180
.EQU MYRAMPLAYSTART = 0x0072
.EQU MYRAMPLAYEND = 0x017E

.DEF button0downvar = R21
.DEF ADC_SCALE = R25
.DEF T1_SCALE = R20

;Interrupt vector table
rjmp init

.org OC1Aaddr							; Interrupt vector for timer1 output compare match A
rjmp OC1A_isr

;Main code
init:
	ldi r16, HIGH(RAMEND)						; Initiate Stack pointer
	out SPH, r16
	ldi r16, LOW(RAMEND)
	out SPL, r16

	ldi r16, 0x00
	out EEARH, r16
	ldi	r16, 0x10						; Load oscillator calibration byte
	out	EEARL, r16
	ldi	r16, (1<<EERE)
	out	EECR, r16
	in	r16, EEDR
	out	OSCCAL, r16	

	ldi r16, 0xDD						;ADC_SCALE initial value
	out EEARL, r16
	ldi r16, (1<<EERE)
	out EECR, r16
	in ADC_SCALE, EEDR
	andi ADC_SCALE, 0b111

//	ldi ADC_SCALE, 0b100

	ldi r16, (1<<PB1) | (1<<PB0)		; Set PB1,PB0 as outputs... PB2, PB3, PB4 as inputs
	out DDRB, r16

	ldi r16, (1<<PB4) | (1<<PB3)		; Pullup PB3 and PB4
	out PORTB, r16

		; Enable Timer/Set PWM clock prescaler to CK (8MHz PWM clock)
		; Set PWM mode: set OC1A pin on compare, disconnect ~OC1A pin
		; Enable PWM

	ldi r16, (1<<CS10) | (1<<CTC1) | (1<<COM1A0) | (1<<COM1A1) | (1<<PWM1A)
	out TCCR1, r16						

	ldi r16, 0xFF						; Set PWM top value: OCR1C = 0xFF
	out OCR1C, r16				

	ldi r16, (1<<MUX0) | (1<<ADLAR)		; Setup ADC: left-adjust and ADC1 (PB2)
	out ADMUX, r16

	clr r17
	clr r18
	ldi XH, high(MYRAMSTART)			; Set up X to point to the beginning of SRAM
	ldi XL, low(MYRAMSTART)



	ldi r16, (1<<WDCE) | (1<<WDE) 		;Set up Watchdog timer
	out WDTCR, r16
	ldi r16, (1<<WDE) | (0<<WDP3) | (0<<WDP2) | (1<<WDP1) | (1<<WDP0)
	out WDTCR, r16


	ldi YL, LOW(MYRAMPLAYSTART)				; Set playback pointer Y
	ldi YH, HIGH(MYRAMPLAYSTART)


	ldi r16, (1<<OCIE1A)				; Disable Timer1 OVF interrupt
	out TIMSK, r16

	sei									; Enable global interrupts

	

//*****************************************************************//
//************************ MAIN LOOP ******************************//

idle:

	SBIS PINB, 4
	rjmp button0down
	CBR button0downvar, 1

	SBIS PINB, 3
	rjmp button1down
	CBR button0downvar, 2

done3:
										; ADC enable, start conversion
	ldi r16, (1<<ADEN) | (1<<ADSC) | (1<<ADIF)
	or r16, ADC_SCALE
	out ADCSRA, r16
	
	ldi XH, HIGH(MYRAMSTART)			; Reset X to the start of SRAM
	ldi XL, LOW(MYRAMSTART)

	WDR

waitADC:
	in	r16, ADCSRA						; Wait for ADC to be ready with data
	sbrs r16, ADIF	
	rjmp waitADC 	
	nop									; Wait some extra cycles...
	nop
	nop
	nop
	nop
	nop
	
	in r17, ADCH						; Grab the ADC value

	ldi r16, (1<<ADEN) | (1<<ADSC) | (1<<ADIF)	;Start and ADC Conversion
	or r16, ADC_SCALE
	out	ADCSRA, r16	

	ldi r18, LOW(MYRAMEND)				; Compare SRAM write pointer X to the limits of the RAM
	ldi r19, HIGH(MYRAMEND)
	CP r19, XH
	CPC r18, XL
	BREQ idle							; exit if we have reached the end of RAM 

	st X+, r17							; Store it into SRAM!!


	rjmp waitADC


button0down:

	WDR
	SBRC button0downvar, 0
	rjmp idle
	SBR button0downvar, 1

	dec ADC_SCALE						; roll ADC_SCALE between 0 and 7
	ANDI ADC_SCALE, 0b111				
	
	//write ADC_SCALE to eeprom
	ldi r16, 0xDD						;ADC_SCALE initial value
	out EEARL, r16

	out EEDR, ADC_SCALE

	ldi r16, (1<<EEMPE)
	out EECR, r16
	ldi r16, (1<<EEPE)
	out EECR, r16


	rjmp idle

button1down:
	WDR
	inc ADC_SCALE
	ANDI T1_SCALE, 0b111
rjmp done3
//	SBRC button0downvar, 1
//	rjmp idle
//	SBR button0downvar, 2





OC1A_isr:
	ldi r22, LOW(MYRAMPLAYEND)
	ldi r23, HIGH(MYRAMPLAYEND)
	CP r22, YL
	CPC r23, YH
	BRNE readsram						; Read from SRAM if Y is smaller than RAMEND

	ldi YL, LOW(MYRAMPLAYSTART)				; ...otherwise reset Y to the start of SRAM
	ldi YH, HIGH(MYRAMPLAYSTART)

readsram:
	ld r24, Y+
	out OCR1A, r24


	reti